Solid state imager sensors operate by converting incident optical energy into charge that is spatially correlated to the incident optical image. In order to reconstruct and/or store the image in another medium, the photo-charge is typically converted into a voltage. As illustrated in FIGS. 1A-1B, this is usually accomplished by transferring the photo-charges from a storage region by means of an output gate 1, of a CCD image sensor for example, onto an integrated capacitor realized by a floating diffusion. A floating diffusion region 9 is connected to a gate electrode 3 of a MOS transistor which is part of the output amplifier. The MOS transistor also comprises a source region 4 and a drain region 5. During operation of an image sensor having parallel channels, charge samples are transferred to the floating diffusion region 9, which is electrically coupled to the gate electrode 3 of the MOS transistor. The voltage on the gate electrode of the output transistor is the input voltage to the output amplifier and is determined by the pixel charge transferred onto the floating diffusion. In order to prevent the voltage at the gate electrode 3 of the MOS transistor from being influenced by pixel charge samples that have previously been applied to the floating diffusion, a reset gate 7 is used to reset the floating diffusion to a reference potential determined by the reset drain 8 at a predetermined time after each pixel sample charge has been deposited on the floating diffusion. Each pixel charge is converted to a voltage by the relationship, V=Q/C; where V is voltage, Q is charge; and C is the capacitance of the floating diffusion.
In any application where light levels are inherently or preferably low, (such as copiers), it is desirable to make this capacitance as small as possible so that the sensitivity, defined as dV/dQ, is large hence providing an adequate output voltage swing with lower illumination levels. The floating diffusion structure 2 is typically formed by a shallow implant 9 and contacted via metallization 10 that connects the floating diffusion region 9 to the gate electrode 3 of the MOS transistor, which is part of an amplifier. Such a system is described for example in U.S. Pat. No. 4,594,604 issued to Kub on Jun. 10, 1986. The net capacitance of such a floating diffusion is determined by the capacitance between the output gate electrode 1 of the associated solid state imager and the floating diffusion region 9, the capacitance between the reset gate electrode 7 and the floating diffusion region 9, the input capacitance of the amplifier, the parasitic capacitance associated with the metallization interconnect 10 and the connection to the MOS transistor gate electrode, and the junction capacitance of the floating diffusion region 9.
With such conventional systems, the parasitic capacitance is increased by the fact that this metallization interconnect 10 should be long enough to permit a connection with the transistor out of the active channel region 12 of the transistor (connection pad 11). In addition, the floating diffusion region is not the minimum geometry realizable due to the contact and interconnect scheme, hence the minimum junction capacitance is limited by the contact patterning resolution and the overlap required for alignment tolerances.
One method to minimize the net node capacitance of the floating diffusion was presented by K. Miwada et al "A 100 MHz Data Rate, 5000-Element CCD Linear Image Sensor With Reset Pulse Level Adjustment Circuit" IEEE International Solid-State Circuits Conference, Technical Digest, pp 168-169, 275, 1992. According to this approach, as illustrated in FIGS. 2A-2B of the drawings, the gate electrode 3 of the transistor is directly connected to the floating diffusion region 9 through a "buried contact". One possible process used to produce such a floating diffusion structure is illustrated in FIGS. 3A-3G of the drawings. In FIG. 3A, a gate oxide 30 is grown on a substrate 31 of a given conductivity type. In FIG. 3B, a buried contact 32 is patterned with photoresist 33 and etched. In FIG. 3C, a floating diffusion region 9 of a conductivity type opposite to the one of the substrate 31 is implanted or diffused. In FIG. 3D, a gate electrode 3 is deposited, patterned with a photoresist 34 and etched, the gate electrode 3 being in direct contact with the floating diffusion region 9. Also, during this step, the reset gate electrode 7 as well as the output gate electrode 1 of the image sensor can be formed. In FIG. 3E, the reset drain region 8 is patterned (photoresist 36) and implanted with an implant of the same conductivity type as the one of the floating diffusion region 9. During this implanting step the source/drain regions (not shown) of the MOS transistor are also implanted. In FIG. 3F, a dielectric 37 is deposited, patterned (photoresist 38) and etched to form contacts 39. In FIG. 3G, metallization 40 is deposited, patterned and etched for the above mentioned contacts. Even if such an approach eliminates the need for any metal interconnect between the floating diffusion 2 and the gate 3 of the MOS amplifier, it has some disadvantages. First it requires the addition of an extra mask and lithography sequence to the baseline image sensor process, i.e. to the standard single, double or more, level poly imager process. It also requires either direct contact of the gate oxide 30 with photoresist 33, or additional process steps to prevent direct contact. As a result, the yield and cost of the device is adversely affected.